This invention relates to command operation of DRAMs, which avoids use of refresh commands requiring routine cessation of read and write accesses.
Synchronous DRAM chips, that is having a synchronous interface with all signals registered on a common (say positive) edge of a clock signal, are usually organized internally into several banks, typically four, and capable of operating in burst mode. Command codes entered on command inputs determine the type of operation and address inputs determine the bank as well as the row and column to which the command is directed.
Arranging the memory into banks enables more efficient access as it enables one bank to be prepared for an access while another is undergoing access.
It is also more efficient to operate DRAMs in burst mode where several locations are accessed in sequence for a single read or write command. With many applications such as data communications or video processing where large blocks of sequential data are moved in and out of memory, bursts of 8 or more clock cycles may be used which means that operation on one bank will take place for those cycles before another bank is accessed. Further, the same bank may be repeatedly accessed.
As with all DRAM chips it is necessary to refresh the memory cells which is usually done on a row by row basis in a cyclic manner under the control of a timer that keeps track of when refresh is due. A 128 Mb SDRAM configured as a quad-bank DRAM typically has 134,217,728 cells (or bits), each bank having 33,554,432 bits organized as 4,096 rows by 256 columns by 32 bits. Typically each of the 4096 rows of each bank must be refreshed every 64 ms, which is done either by doing a burst of 4096 refresh operations to each bank every 64 ms or, if refresh is performed in a distributed manner, a refresh command to a different row in each bank every 15.625 xcexcs.
With these multi-bank SDRAM chips, refresh operation is conducted simultaneously on all banks during which time no data operations are carried out. Before the refresh can begin all the rows that were open for data operations have to be closed, by way of a PRECHARGE. The open rows may be in more than one bank as there may be read/write access underway in one bank and a second bank opened ready for the subsequent access. A third bank (used for the previous access) may already be in the process of being closed by a previous PRECHARGE instruction.
When the timer indicates refresh is due, data operations must be completed or interrupted. The internal control could provide for either. However, in particular when operating on long bursts it may not be possible to complete the burst without over-running the refresh due time and so interruption is necessary. To avoid complexity in the controller the refresh required indication from the timer is set to precharge (close) all open banks, resulting in some loss of current data operations.
Closing all the banks to data operations for the duration of the refresh results in loss of bandwidth. The time that the SDRAM is unavailable is the sum of the time taken to close (precharge) the open banks, plus the refresh time, plus the time to open them again.
It is desirable to be able to refresh without suspending data operations.
Techniques for hiding refresh operations have been proposed in less complex systems that do not have multi-bank interleaving. These proposals have required either additional hardware to carry separate lines for refresh commands or software modification that consumed CPU bandwidth.
The present invention is based on the surprising realization that despite the complexity of interleaved multi-bank data access operations, burst operation enables most if not all the refresh operations to be simultaneously interleaved (i.e. run in parallel) with continuing data operations.
According to the invention there is provided a method of refreshing an SDRAM chip having a memory internally configured in a plurality of banks, the method comprising: issuing data operation commands in burst mode whereby at least some command intervals are available for other operation commands, issuing in one of said available command intervals a command to open a row in a bank other than the bank under access in the current burst, after a predetermined interval and before said bank other than the bank under access is required for a data operation, issuing in another of said available command intervals a command to close the opened row. The closing of the row is usually accomplished by closing the bank.
The invention also provides apparatus for generating commands for refreshing an SDRAM that is internally configured in a plurality of banks and operates in burst sequences, the apparatus comprising: an address generator for establishing refresh addresses of row and bank due for refresh; a multiplexer for sequencing the refresh addresses with data addresses so that the refresh address is sequenced to a bank that will not be accessed for a data burst, a controller for inserting into burst command intervals an open command to the refresh address and after a predetermined minimum interval inserting into burst command intervals a close command to the refresh address, and in which the open and close operations are arranged to be completed before the bank of the refresh address is next addressed by a data access command.
The present invention utilises standard SDRAM layout and data and command buses, but does not utilise the usual system refresh commands. Instead of refresh commands a command such as the commonly termed xe2x80x9cactivexe2x80x9d command which would normally be used to open a row ready for a data operation is used, followed by a command such as the commonly termed xe2x80x9cprechargexe2x80x9d command to close the row again without any data operation being performed. This utilises existing command operations and command and address buses to one of the banks not undergoing data operations and can be run in parallel with data access operations and their attendant interleaved operations on other banks.